Schematic

For signals I try to use the same naming convention as digital. So the signals start either with B for Bus, R for Receive and T for Transmit and have an optional L at the end of the name if they are active low.

The first pages shows the section with the signals I receive from the Q-Bus. As already mentioned I’m using 74HC4049 and operate them with 3.3V. At this voltage the 74HC4049 have a threshold of approximatively 1.7V, which is the standard for Q-Bus receivers. I use a SMT LDO regulator in a SOT-23 package. I know that I said through hole ICs only but I think a SOT-23 is acceptable.

The next page shows the lower 16 bits of the multiplexed address/data bus. The Q-Bus is bidirectional but as I only use receivers and transmitters and no transceivers, like the DC005, I end with 16 bits receive and 16 bits transmit data signals.

The next section shows the remaining signals I need to transmit to the Q-Bus. For each Q-Bus signal I need to be able to transmit and receive I end up with two signals the emulator has to interface with. This is the main reason I had to add a second CPLD when switching from a single CPDL in a TQFP-100 package with 80 pins available. to a PLCC-84 package with only 64 pins available.

When using two CPLDs I had to split the function blocks of the Q‐Bus interface from the first RLV12 Emulator. I tried to avoid having the same signal being required by both CPLDs as this would require even more pins. Mainly by placing the receive path to the ATF1504 and the transmit path to the ATF1508 the only Q‐Bus signals required by both CPLDs are RSYNC and RWTBT. Also only very few signals run between the CPLDs themselves. All the control functions, state machines and bus logic was left in the larger CPLD. Of course both CPLDs will share the interface towards the MCU.

The rest of the schematic is very simple, there is the MCU and the IDC-34 connector for the ribbon cable that runs to the break-out board

and of course the Q-Bus interface